Introduction#
Brief Overview#
A rough overview of floorplan in OpenROAD:
- The content of the floorplan is a complete planning and design of the internal interfaces of the chip, including:
- Chip size (
ifp):- initializes floorplan constraints, die/core area, and makes tracks.
- Chip IO (
ppl,pad)- pin placement: Place pins on the boundary of the die on the track grid to minimize net wirelengths.
- Chip-level Connections: either place an IO ring around the boundary of the chip and connect with either wirebond pads or a bump array.
- macro placement (
mpl,mpl2)- The macro placer places macros/blocks honoring halos, channels and cell row “snapping”.
- Power planning (
pdn)- PDN Generation: specifies a small set of power grid strategies applied to the design, such as the number of layers used, stripe width, and spacing, and then lets the utility generate the actual metal strips.
- Chip size (
- The floorplan relates to the chip's timing convergence, routing smoothness, power stability, and yield.
- From floorplan to completed placement generally takes up 1/3 of the entire physical implementation time.
Terminology#
- Bond Pad is a critical contact point for electrical connection between the chip and the external package, ensuring the transmission of electrical signals and power distribution. Its layout directly affects packaging processes, signal integrity, and chip size, making it an important aspect of floorplan design.
- Bump Array is a key structure for electrical, mechanical, and thermal connections between the chip and the package substrate or PCB, widely used in Flip-Chip and 3D IC packaging. The floorplan stage requires precise planning of the Bump Array's position, density, and distribution to optimize signal performance, power integrity, and thermal management.
Content and Goals of Floorplan Planning#
The floorplan is the first step in the physical design of the chip, used to determine the positions of the core area, macro cells, IO cells, as well as routing resources and power planning to optimize chip performance and area.
The main goals of the floorplan include:
- Area: Ensure routing while minimizing the cost of finished products.
- Timing Convergence: Estimate chip delays to determine if SDC requirements can ultimately be met, achieving timing convergence.
- Stability: Ensure uniform power distribution within the chip and sufficient power supply.
- Routing Efficiency: While ensuring smooth routing, minimize the length of the routes, thereby reducing interconnect delays and effectively improving chip performance.
Placement and Power Supply of I/O Interface Units#
- TODO
Floorplan Planning Scheme and Delay Estimation#
Before performing the floorplan, delay analysis is conducted on the synthesized netlist using a zero-load model to evaluate timing. If the timing is poor, the netlist should be optimized.
The timing and delay estimation methods during the floorplan stage depend on the chip design methodology, namely 1. bottom-up flattening silicon virtual prototyping (SVP); 2. top-down hierarchical design.
PS: When the design is around 5 million gates, consider adopting a hierarchical design scheme.
Flattened Design#
In flattened design, after placing multiple floorplans, STA is used to estimate the delay of the entire chip, and then timing violations (negative slack) are used to evaluate the effects of different floorplans.
Since interconnects have not yet been established at this stage, delays can only be estimated through WLM (the term "only" is questionable; WLM is a statistical model that estimates load capacitance and line length to preliminarily predict line delays).
WLM (Wire Load Model) is a model used in the early stages of the RTL-to-GDSII flow (such as the synthesis stage) to estimate signal net capacitance, resistance, and delay, primarily based on circuit scale, net fanout, and statistical data.
Hierarchical Design#
Hierarchical design can be roughly divided into three steps: top-level chip design planning, submodule partitioning and implementation, and top-level chip assembly implementation.
In timing budgeting, the timing of the entire chip needs to be analyzed first.
- TODO
Module Placement and Routing Channels#
Module placement is based on floorplan planning, and the results of module layout will directly impact the expected goals of the initial floorplan, where the completion of routing is assessed through routing channel analysis.
A routing channel is the space between two or more tracks, standard cells cannot be placed on the channel. Additionally, a halo (reserved for dedicated routing) is usually left around macros where standard cells are not allowed.
- Routing Channel: The reserved space for routing channels in the layout, typically found in gaps between macro cells or cells.
- Routing Track: The regular grid lines on the routing layer, with each track representing a position where signal lines can be placed.
In hierarchical design, channels are categorized into T and L shapes based on their geometry. When two submodules are spaced far apart, a feedthrough channel must also be defined to meet timing and routing requirements.
A row-based routing method is introduced in hierarchical design, which is the channel-less partitioning method shown in figure b. Figure a shows channel-based partitioning, and figure c shows a hybrid method.