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Digital Integrated Circuit Physical Design 1.2: Design Flow

#IC#理论#物理设计12
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The document discusses three physical design methodologies in chip design: 1. **Flat Physical Design**: This approach involves designing from the bottom up using standard cells, allowing for comprehensive visibility of all cells, which aids in global timing analysis and optimization. Advantages include easier timing convergence and intuitive handling for small designs. However, it has significant drawbacks for large designs, such as high computational demands, challenges in resource allocation, longer design cycles, and inefficient resource utilization. 2. **Hierarchical Physical Design**: This method divides large designs into smaller blocks for independent layout and routing, focusing on complex timing modules to shorten convergence cycles and localize timing issues. It is more suitable for large-scale designs but limits cross-module optimization. 3. **Silicon Virtual Prototyping**: This approach segments the design during the layout phase and uses fast approximate routing methods. It employs lumped capacitance models during RC extraction for quick convergence assessments, with a margin of error of about 5%-10%. In summary, flat design is ideal for small designs with global optimization but is resource-intensive, while hierarchical design is better for large projects with localized timing issues. Silicon virtual prototyping offers speed and efficiency in early design stages for complex chips.

Flattened Physical Design#

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Flattened physical design: physical design based on standard cells from bottom to top, including designing transistors, simulation, establishing layouts, and then simulating and modeling logic gate cells.

Advantages:#

  1. Comprehensive Information View: Flattened design allows designers to see information for all cells in the chip, which helps with global timing analysis and optimization.
  2. Easier Timing Convergence: Since the entire chip layout can be observed, timing convergence is relatively easier to handle, and any timing violations that occur are also relatively easier to resolve.
  3. Intuitiveness: For small designs, flattened design can be intuitively processed and optimized due to the smaller computational load.

Disadvantages:#

  1. High Computational Load: For large designs, flattened design requires handling a large amount of computation, which may lead to significant consumption of computational resources.
  2. Difficult Personnel Allocation: In large projects, it is challenging to effectively allocate personnel and fully utilize resources in flattened design, which may lead to extended design cycles.
  3. Long Design Cycle: Due to the high computational load and personnel allocation issues, flattened design may result in a longer overall chip design cycle, affecting the time to market for the chip.
  4. Inefficient Resource Utilization: In large designs, it is difficult to fully utilize all available resources in flattened design, which may lead to inefficiencies.

Overall, flattened physical design has its advantages when handling small or timing-critical designs, but its disadvantages become apparent when facing large and complex integrated circuit designs, especially in terms of computational resource consumption and design cycle.

Hierarchical Physical Design#

Hierarchical physical design divides the large design into several partitioned blocks during physical design, performing independent layout and routing for each partitioned block, and completing assembly design at the top level. This method focuses on handling timing-complex modules, shortening the design convergence cycle, and localizing timing issues.

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Silicon Virtual Prototype Design#

This method considers partitioning the entire design during the layout phase and uses fast approximate trial routing methods during routing. When performing RC extraction, a lumped capacitance model can be used for quick design convergence evaluation, with a discrepancy of about 5%-10% compared to the final results.

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Summary#

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Flattened physical design: bottom-up, intuitive and accurate, but with a long cycle. Suitable for small-scale designs, enabling global optimization but with high resource demands.
Hierarchical physical design: top-down, block partitioning, localizing timing issues. Suitable for large-scale designs, reducing complexity through modularization, but with limited cross-module optimization.
Silicon virtual prototype design: fast, using experimental routing methods during routing. Used in early design stages, evaluating physical implementation effects through efficient modeling, supporting rapid decision-making for complex chips.

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